Abstract - In this paper, a power/performance optimized dual-mode mode is presented. This dual operating mode SRAM compensates for the delay in optimized speed mode by cutting off the precharge voltage in cases where the sense amplifiers are slower than expected and a same approach for optimized power mode is applied in which the delay time access is increased. at each iteration. The proposed scheme with a macro-cell representing a column of 512 cells is implemented in 0.18um CMOS technology. A 45% improvement in readout frequency is confirmed in power-optimized mode and a 2x improvement in failure rate is also achieved compared to conventional schemes using simulation and measurement results.I. INTRODUCTIONIntegrated SRAMs are extremely important components of modern chips. They are used in caches, register files, FIFOs, etc. Increasing CPU and DSP speed reinforces the need to design higher performance SRAM. On the other hand, portable products such as PDAs and cell phones must conserve energy very aggressively. Balancing the tradeoffs between small area, low power, and fast reads/writes is a critical part of any SRAM design optimization. Lower power consumption is achieved through performance degradation and higher performance is associated with higher power consumption. However, in this article, depending on the CPU workload and the power source, whether plugged in or connected to the battery, the power or performance is optimized independently. Read access time is strongly related to the sense amplifier, one of the most critical circuits at the edge of a memory. Using voltage-mode sense amplifiers results in speed limitation due to the high capacitance of the bitlines. Current mode sense amplifiers, on the other hand, can be great...... middle of paper ......, IEEE Journal of, vol.33, no.8, pp.1208-1219, August 1998 .[10. ]. Houle, R.; , "Simple Statistical Analysis Techniques for Determining Minimum Sense Amplifier Setting Times", Custom Integrated Circuits Conference, 2007. CICC '07. IEEE, vol., no., pp. 37-40, September 16-19, 2007[11]. Aitken, R.; Idgunji, S.; , "Worst-Case Design and Margin for Embedded SRAM", Design, Automation & Test in Europe Conference and Exhibition, 2007. DATE '07, vol., n°, pp.1-6, April 16-20, 2007.[12 ]. Sharifkhani, M.; Sachdev, M.; , “SRAM Cell Stability: A Dynamic Perspective”, Solid-State Circuits, IEEE Journal of, vol.44, no.2, pp.609-619, February 2009[13]. Attarzadeh, H.; SharifKhani, M.; Jahinuzzaman, SM; , "A scalable offset-cancelled current/voltage sense amplifier", Circuits and Systems (ISCAS), Proceedings of the 2010 IEEE International Symposium on , vol., no., pp.3853-3856, May 30, 2010-June 2 2010